The present invention relates to a semiconductor device, and can be preferably used in a semiconductor device having, for example, a built-in non-volatile memory.
Japanese Patent Publication No. 5265898 (Patent Document 1) describes a semiconductor device including a first non-volatile memory cell and a second non-volatile memory cell that are arranged adjacent to each other. A capacitive element of the first non-volatile memory cell is formed in a first active region, and both a read-out element of the first non-volatile memory cell and that of the second non-volatile memory cell are formed in a third active region. Additionally, both a writing/erasing element of the first non-volatile memory cell and that of the second non-volatile memory cell are formed in a second active region. Additionally, a capacitive element of the second non-volatile memory cell is formed in a fourth active region.